1. Field of the Invention
This invention relates to a semiconductor memory cell with a floating gate, more particularly to a method for manufacturing a semiconductor memory cell with a floating gate.
2. Description of the Related Art
In semiconductor memory cells which have floating gates and which are nonvolatile, information that is stored is not lost when the power supply is removed. Memory cells of this type include an erasable nonvolatile memory cell, such as a split gate EPROM (erasable programmable read only memory). In order to reduce an erase voltage of the erasable nonvolatile memory cell, a conventional split gate EPROM having floating gates has been provided. The floating gates of the conventional split gate EPROM is formed with tip along the edge of floating gate thereof by the well known LOCOS process such that a high electric field is generated between the polysilicon layers of the conventional split gate EPROM to provide an effective tunneling of the electrons from a floating gate to a control gate, thereby reducing the erase voltage.
FIGS. 1 to 5 depict the steps of a conventional method for manufacturing the aforementioned conventional split gate EPROM having a floating gate with a predetermined length and source and drain regions. As illustrated in FIG. 1, a thin oxide layer 11 is grown over a semiconductor substrate 10. A first polysilicon layer 12 is deposited over the thin oxide layer 11. A silicon nitride layer 13 is deposited over the first polysilicon layer 12. Then, as illustrated in FIG. 2, the silicon nitride layer 13 is masked and etched down to the first polysilicon layer 12 so as to form oxide receiving grooves 131 in the silicon nitride layer 13. The dimension of the floating gates of memory cell is equal to dimension of the oxide receiving grooves. The oxide receiving grooves 131 overlap respective floating gate regions to be defined on the first polysilicon layer 12. As illustrated in FIG. 3, a polysilicon oxide layer 14 is grown in each oxide receiving groove, and the silicon nitride layer is removed. The first polysilicon layer 12 is etched with the polysilicon oxide layer 14 serving as a mask so as to form the floating gates with tip along the edge of floating gate. As illustrated in FIG. 4, a gate oxide layer 15 is grown over the floating gates and a second polysilicon layer 16 is deposited over the gate oxide layer 15. The second polysilicon layer 16 is masked and etched to define control gates having longitudinal axes parallel to those of the floating gates. Each of the control gates further has a first edge positioned above the respective floating gate and a second edge positioned on the gate oxide layer 15. As illustrated in FIG. 5, impurities are implanted in the drain and source regions, 18 and 17. The conventional split gate EPROM is completed by using standard CMOS processes, such as by providing a passivation layer (not shown) and metallization and electrodes that allow conduction of signals to and from external circuitry.
As illustrated in FIGS. 6A and 6B, the conventional split gate EPROM manufactured by the aforementioned conventional method will encounter a problem on the pattern definition of the floating gates during the scaling down of the EPROM since the definition of oxide receiving groove portions of the floating gates will cause a rounding effect resulting from diffraction, thereby resulting in cell leakage because of reducing effective channel length of floating gate.